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53
9151AINDCO07/09
ATA8742
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. See the section Digital Input Enable and Sleep Modes on page 76 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
CC
/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
CC
/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). See
DIDR0  Digital Input Disable Register 0 on page 172 for details.
15.8   Register Description
15.8.1
MCUCR  MCU Control Register
The MCU Control Register contains control bits for power management.
"  Bit 5  SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
"  Bits 4, 3  SM1..0: Sleep Mode Select Bits 2..0
These bits select between the three available sleep modes as shown in Table 15-2 on page 53.
Note:
1.  Only recommended with external crystal or resonator selected as clock source
"  Bit 2  Res: Reserved Bit
This bit is a reserved bit in the ATtiny24/44/84 and will always read as zero.
Bit
7
6
5
4
3
2
1
0

PUD
SE
SM1
SM0

ISC01
ISC00
MCUCR
Read/Write
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Table 15-2.    Sleep Mode Select
SM1
SM0
Sleep Mode
0
0
Idle
0
1
ADC Noise Reduction
1
0
Power-down
1
1
Standby
(1)
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